peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 252

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

ALLS…
XDU…
XMB…
XLSC…
XPR…
Data Sheet
All Sent
This bit is set if the last bit of the current frame has been sent out
completely and XFIFO is empty.
Transmit Data Underrun
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO and no XME was
issued.
Note: Transmitter and XFIFO are reset and deactivated if this
Transmit Multiframe Begin
This bit is set every 2 ms with the beginning of a multiframe
transmission and is related to the internal transmit line interface
timing.
After setting this bit, registers XS1...16 are copied into the transmit
shift registers. The registers XS1...16 are now ready for the next data
and have to be updated; otherwise the contents is retransmitted
during the next multiframe. A wait time of 3µs has to be observed
between reading of XMB = 1 and start of reprogramming XS1...16.
Transmit Line Status Change
XLSC is set with the rising edge of the bit FRS1.XLO or with any
change of bit FRS1.XLS.
The actual status of the transmit line monitor can be read from the
FRS1.XLS and FRS1.XLO.
Transmit Pool Ready
A data block of up to 32 bytes can be written to the transmit FIFO.
XPR enables the fastest access to XFIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
condition occurs. They are re-activated not before this
interrupt status register has been read. Thus, XDU should not
be masked via register IMR1.
252
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07