peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 34

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 3
Pin No.
80
72
Data Sheet
Symbol
SYNC2
RCLK
Pin Definitions - Clock Generation (cont’d)
Input (I)
Output (O)
Supply (S)
I
O + PU
Function
Clock Synchronization 2
Secondary reference clock for internal transmit
clock generation.
The clock frequency is 2.048-MHz (E1) or 2.048/
1.544-MHz (T1/J1).
This function is selected by setting LIM3.ESY=1
Note: This pin contains multiple functions, see
Receive Clock
extracted from the incoming data pulses.
Clock frequency: 2048 kHz (E1) or
1544 kHz (T1/J1)
In case of loss of signal (LOS) the RCLK is
derived from the clock that is provided on
XTAL1.
If LIM0.ELOS is set, RCLK is set high in case of
loss of signal (FRS0.LOS = 1).
If NRZ mode is selected, RCLK is the buffered
RCLKI clock.
34
also ROID and XSIG.
Pin Descriptions
FALC-LH V1.3
PEB 2255
2000-07