peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 195

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

SIM…
Framer Mode Register 1 (Read/Write)
Value after RESET: 00
MFCS…
AFR…
ENSA…
Data Sheet
FMR1
MFCS
7
Alarm Simulation
0…
1…
Only valid if CRC multiframe format is selected (FMR2.RFS1/0=10).
A transition from low to high initiates the resynchronization procedure
for CRC-multiframe alignment without influencing doubleframe
synchronous state. In case, “Automatic Force Resynchronization”
(FMR1.AFR) is enabled and multiframe alignment can not be
regained, a new search of doubleframe (and CRC multiframe) is
automatically initiated.
Only valid if CRC multiframe format is selected (FMR2.RFS1/0=10).
If this bit is set, a search of doubleframe alignment is automatically
initiated if two multiframe patterns with a distance of n
not been found within a time interval of 8 ms after doubleframe
alignment has been regained.
0…
1…
Multiframe Force Resynchronization
Automatic Force Resynchronization
Enable S
Note:MFCS is not reset automatically.
AFR
H
Normal operation.
Initiates internal error simulation of AIS, loss of signal, loss of
synchronization, remote alarm, slip, framing errors, CRC
errors, and code violations. The error counters FEC, CVC,
CEC1 are incremented.
Normal operation. The S
XSW.XY0…4 and written to bits RSW.RY0…4.
S
registers XSA4...8. In addition, the received information is
written to registers RSA4...8. Transmitting of the contents of
registers XSA4...8 is disabled if one of time slot 0 transparent
modes is enabled (XSP.TT0 or TSWM.SA4...8).
a
-bit register access. The S
ENSA
a
-Bit Access via Register XSA4...8
PMOD
195
XFS
a
-bit information is taken from bits
a
-bit information is taken from the
ECM
IMOD
FALC-LH V1.3
XAIS
E1 Registers
0
PEB 2255
2 ms have
2000-07
(1B)