peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 64

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

is given out via port RDO. If the receive buffer is bypassed, data is clocked off with RCLK
instead of SCLKR.
In one frame or short buffer mode the delay through the receive buffer is reduced to an
average delay of 128 or 46 bits. Slips are performed in all buffer modes except the
bypass mode. After a slip is detected the read pointer is adjusted to one half of the
current buffer size.
The following table gives an overview of the receive buffer operating mode.
Note: Combinations of SIC1.RBS1...0 and LOOP.SFM other than described are not
•.
Table 12
SIC1.RBS1...0
11
LOOP.SFM = 0
10
LOOP.SFM = 0
01
LOOP.SFM = 0
00
LOOP.SFM = 1
00
LOOP.SFM = 0
1)
Data Sheet
In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK.
allowed. The use of LOOP.SFM = 1 is not recommended, but possible for
FALC
®
54 compatibility.
Receive Buffer Operating Modes (E1)
Buffer Size
bypass
short buffer
1 frame
1 frame
2 frames
1)
TS Offset programing
(RC1...0)
RFM (SYPR = output) must
be selected; value of
RC1...0 determines the
position of RFM
RFM (SYPR = output) must
be selected; value of
RC1...0 determines the
position of RFM
RFM (SYPR = output) must
be selected; value of
RC1...0 determines the
position of RFM
SYPR is input and
determines the frame
position together with
RC1...0 offset.
SYPR is input and
determines the frame
position together with
RC1...0 offset.
64
Functional Description E1
Slip performance
no slips
yes
yes
Slip conditions are
detected and reported,
but no slip is performed.
Slips have to be initiated
by software
(reprogramming of
RC1...0).
yes
Slips are performed on
the frame boundary
FALC-LH V1.3
PEB 2255
2000-07