peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 223

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

System Interface Control 2 (Read/Write)
Value after RESET: 00
FFS …
SSF …
SRFSO…
Data Sheet
SIC2
FFS
7
Force Freeze Signaling
Setting this bit disables updating of the receive signaling buffer and
current signaling information is frozen. After resetting this bit and
receiving a complete superframe updating of the signaling buffer is
started again. The freeze signaling status could be also automatically
generated by detecting the Loss of Signal alarm or a Loss of CAS
Frame Alignment or a receive slip (only if external register access via
RSIG is enabled). This automatic freeze signaling function is logically
ored with this bit.
The current internal freeze signaling status is available in register
SIS.SFS.
Serial Signaling Format
Only applicable if pin function R/XSIG is selected.
0…
1…
0…
1…
Select Receive Frame Sync Output
SSF
H
Bits 1...4 in all time slots except time slots 0 +16 are cleared.
Bits 1...4 in all time slots except time slots 0 +16 are set high.
Pin SYPR: Input
Pin SYPR: Output
Setting this bit disables the timeslot assigner. With register
RC1/0 the receive frame marker could be activated during any
bit position of the current frame. This marker is active high for
2.048 MHz cycle and is clocked off with the falling edge of
SCLKR or RCLK if the receive elastic store is bypassed.
If no SYPR has been activated since RESET or software reset
CMDR.RES the outputs of the receive system interface
assume an arbitrary alignment.
Calculation of the value X of the “Receive Counter Offset”
register RC1/0 depends on SCLKR and on the bit position BP
which should be marked:
X = (2 + 2BP) mod 512, for SCLKR = 2.048 MHz
223
FALC-LH V1.3
SRFSO
E1 Registers
0
PEB 2255
2000-07
(3D)