peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 98

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

4.6.3
To perform an effective circuit test a payload loop is implemented. The payload loop
back (FMR2.PLB) loops the data stream from the receiver section back to transmitter
section. The looped data passes the complete receiver including the wander and jitter
compensation in the receive elastic store and were output on pin RDO. Instead of the
data an AIS (FMR2.SAIS) can be sent to the system interface.
The framing bits, CRC4 and Spare bits are not looped, if XSP.TT0 =0. They are
originated by the FALC
data on pins XL1/2 or XDOP/XDON are clocked with SCLKR/RCLK instead of SCLKX.
If XSP.TT0 = 1 the received time slot 0 is sent transparently back to the line interface.
Data on the following pins are ignored: XDI, XSIG, SCLKX, SYPX and XMFS. All the
received data is processed normally.
Figure 28
Note: Returned data is not multiframe synchronous.
Data Sheet
RL1
RL2
XL1
XL2
Payload Loop Back
Payload Loop (E1)
Clock +
Data
Recovery
®
-LH transmitter. If the PLB is enabled the transmitter and the
Trans.
Framer
RCLK
Rec.
Framer
98
Elast.
Store
Elast.
Store
Functional Description E1
AIS-GEN
MUX
FALC-LH V1.3
PEB 2255
RDO
SCLKR
XDI
SCLKX
ITS09748
2000-07