peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 51

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Figure 9
Each interrupt indication of registers ISR0…3,5 can be selectively masked by setting the
corresponding bit in the corresponding mask registers IMR0…3,5. If the interrupt status
bits are masked they neither generate an interrupt at INT nor are they visible in
ISR0 … 3,5.
GIS, the non-maskable Global Interrupt Status Register, serves as pointer to pending
interrupts. After the FALC
CPU should first read the Global Interrupt Status register GIS to identify the requesting
interrupt source register. After reading the assigned interrupt status registers
ISR0...ISR3 and ISR5, the pointer in register GIS is cleared or updated if another
interrupt requires service.
If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes
inactive.
Updating of interrupt status registers ISR0 … 3,5 and GIS is only prohibited during read
access.
Masked Interrupts Visible in Status Registers
• The Global Interrupt Status register (GIS) indicates those interrupt status registers
• An additional mode can be selected via bit IPC.VIS.
• In this mode, masked interrupt status bits neither generate an interrupt at pin INT nor
This mode is useful when some interrupt status bits are to be polled in the individual
interrupt status registers.
Data Sheet
with active interrupt indications (GIS.ISR0...3,5).
are they visible in GIS, but are displayed in the respective interrupt status
register(s) ISR0...3,5.
Interrupt Status Registers
IMR5
ISR5
®
-LH has requested an interrupt by activating its INT pin, the
IMR3
IMR2
ISR3
ISR2
ISR5
ISR3 ISR2
GIS
51
ISR1
ISR0
Functional Description E1/T1/J1
ISR0
ISR1
IMR0
IMR1
ITS09740
FALC-LH V1.3
PEB 2255
2000-07