pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 14
pef20324
Manufacturer Part Number
pef20324
Description
Multichannel Network Interface Controller With 128 Channels Extended
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF20324.pdf
(63 pages)
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Hardware Reference Manual
1.4
• 128-channel capability
• Symmetrical Rx and Tx Buffer Descriptor formats for faster switching
• Improved Tx idle channel polling process for significantly reducing bus occupancy of
• Dedicated 1024 byte Tx Buffer
• Dedicated 1024 byte Rx Buffer
• Burst capability also on transmit and receive data sections (8 DWORDs)
• Additional PCM modes supported: 3.088 MBit/s, 6.176 MBit/s, 8.192 MBit/s
• 32 Bit / 33 MHz PCI 2.1 master/slave interface;
• Separate Rx and Tx Status Queues in host memory
• Slave access to on-chip registers
• Time Slot-shift capability:
• Software initiated action request (via the Command Register)
• Tx End-of-Packet transmitted-on-wire interrupt capability for each channel
• Tx packet size increased to 64 Kbytes (HDLC mode)
• Rx packet size 8 Kbyte limit interrupt disable
• Tx data TRISTATE
• Synchronized data transfer in TMA mode
• Little/Big Endian data formats
idle Tx channels
this interface can be configured in De-mux mode
(the MUNICH128X provides one set for each of the four HDLC Controllers)
– Programmable from -4 clock edges to +3 clock edges
– Programmable to sample Tx and/or Rx data at either falling or rising edge of clock
for complete transparency when using fractional T1/PRI
relative to the synchronization pulse
Differences to the MUNICH32
TM
control line
14
Introduction
PEB 20324
PEF 20324
04.99