pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 5

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

List of Figures
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 2-1
Figure 3-1
Figure 3-1
Figure 3-2
Figure 5-1
Figure 5-2
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 6-1
Hardware Reference Manual
WRITE Transaction in De-multiplexed Bus Configuration . . . . . . . . . . .51
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
System Integration of the MUNICH128X in PCI-Based System . . . . . .12
System Integration of the MUNICH128X in De-multiplexed System . . .13
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
System Integration of the MUNICH128X in PCI-Based System . . . . . .34
System Integration of the MUNICH128X in De-multiplexed System . . .35
Power-up and Power-down scenarios . . . . . . . . . . . . . . . . . . . . . . . . . .37
Power-Failure scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . .43
PCI Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . .44
PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . . .44
PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Master Single READ Transaction followed by a Master Single
Master Burst WRITE/READ Access in De-multiplexed Bus
PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . .57
5
PEB 20324
PEF 20324
Page
04.99