pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 23

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

Table 2-5
Pin No.
1
22
26
27
147
Hardware Reference Manual
Symbol
IDSEL
DEVSEL
PERR
SERR
REQ
Pin Descriptions by Functional Block: PCI Interface (cont’d)
Type Description
I
s/t/s
s/t/s
o/d
t/s
Initialization Device Select
When MUNICH128X is slave in a transaction, if IDSEL
is active in the address phase and C/BE(3:0) indicates
a Config read or write, the MUNICH128X assumes a
read or write to a configuration register. In response,
the MUNICH128X asserts DEVSEL during the
subsequent CLK cycle.
IDSEL is sampled on the rising edge of CLK.
Device Select
When activated by a slave, it indicates to the current
bus master that the slave has decoded its address as
the target of the current transaction. If no bus slave
activates DEVSEL within six bus CLK cycles, the
master should abort the transaction.
When MUNICH128X is Master, DEVSEL is input. If
DEVSEL is not activated within six clock cycles after
an address is output on AD(31:0), the MUNICH128X
aborts the transaction and generates an INTA.
When MUNICH128X is Slave, DEVSEL is output.
Parity Error
When activated, indicates a parity error over the
AD(31:0) and C/BE(3:0) signals (compared to the
PAR input). It has a delay of one CLK cycle with
respect to AD and C/BE(3:0) (i.e., it is valid for the
cycle immediately following the corresponding PAR
cycle).
PERR is asserted relative to the rising edge of CLK.
System Error
The MUNICH128X asserts this signal to indicate a
fatal system error.
SERR is sampled on the rising edge of CLK.
Request
Used by the MUNICH128X to request control of the
PCI.
REQ is sampled on the rising edge of CLK.
23
Pin Descriptions
PEB 20324
PEF 20324
04.99