pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 30

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

PEB 20324
PEF 20324
Functional Description
3.3.3.1
Tx Block
Transmit Buffer (TB)
The Tx Block of the HDLC Controller contains a 1024 byte buffer (TB) which may be
allocated to all 32 channels of one cove equally (i.e., 2-DWords per channel) or may be
allocated based on superchannel considerations (e.g., 8–DWords per channel for
8 channels).
HDLC Protocol
Bit stuffing, flag generation, flag stuffing and adjustment, and CRC generation (either 16-
bit or 32-bit) are performed.
V.110 and V.30 Protocol
Bit framing from 600 bit/s to 38.4 Kbit/s, automatic generation of the synchronization
pattern, generation of loss of synchronization, programmable E/SX bits (including during
run-time) are performed.
Transparent Mode A
This mode supports slot synchronous, transparent transmission without frame structure.
It provides flag generation, flag stuffing, flag generation in the abort case with
programmable flag, and synchronized data transfer for fractional T1/E1 PRI applications.
Transparent Mode B
This mode supports transparent transmission in frames delimited by 00
flags, shared
H
closing and opening flag, flag stuffing and flag generation in the abort case.
Transparent Mode R
This mode supports transparent transmission with GSM 08.60 frame structure with
automatic 0000
flag generation and support of 40, 39.5, and 40.5 octet frames.
H
Protocol Independence
Channel inversion (data, flags, idle code) follows the format conventions as in CCITT
Q.921.
Hardware Reference Manual
30
04.99