pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 20
pef20324
Manufacturer Part Number
pef20324
Description
Multichannel Network Interface Controller With 128 Channels Extended
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF20324.pdf
(63 pages)
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Hardware Reference Manual
Table 2-4
Pin No.
89
85
86
81
83
82
84
TxD3
TxDEN3
Symbol
RxCLK3
RxD3
RSP3
TxCLK3
TSP3
Pin Descriptions by Functional Block: Port 3 Serial Interface
Type Description
I
I
I
I
O
I
O
Receive Clock 3
The clock input pin used for sampling the data on
RxD3. The MUNICH128X supports the following PCM
clock rates, programmed via the MODE1 register:
T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz;
E1: 2.048 MHz, 4.096 MHz, 8.192 MHz.
Receive Data 3
The data input pin which is sampled using RxCLK3.
Receive Synchronization Pulse 3
The input pin used for Rx PCM frame synchronization;
the synchronization pulse marks the first bit in the
PCM frame.
Transmit Clock 3
The clock input used for clocking out the data on
TxD3. In most applications, the signal that drives this
pin is externally connected to RxCLK3.
Transmit Data 3
Provides the data which is clocked out of the
MUNICH128X by TxCLK3; data is push-pull for active
bits in the PCM frame and TRISTATE for inactive
bits.
Transmit Synchronization Pulse 3
The input pin used for Tx PCM frame synchronization;
the synch. pulse marks the last bit in the PCM frame.
Transmit Data Enable 3
An active low output signal which specifies data on the
TxD3 output pin is valid.
20
Pin Descriptions
PEB 20324
PEF 20324
04.99