pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 9

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

• Bit Processor Functions (adjustable for each channel)
Hardware Reference Manual
– HDLC Protocol
– V.110/X.30 Protocol
– Transparent Mode A
– Transparent Mode B
– Transparent Mode R
– Protocol Independent
– Automatic flag detection
– Shared opening and closing flag
– Detection of interframe-time-fill change, generation of
– Zero bit insertion
– Flag stuffing and flag adjustment for rate adaption
– CRC generation and checking (16 or 32 bits)
– Transparent CRC option per channel and/or per message
– Error detection (abort, long frame, CRC error, 2 categories
– ABORT/IDLE flag generation
– Automatic synchronization in receive direction, automatic generation of
– E/S/X bits freely programmable in transmit direction, may be changed
– Generation/detection of loss of synchronism
– Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s
– Slot synchronous transparent transmission/reception without frame structure
– Flag generation, flag stuffing, flag extraction, flag generation
– Synchronized data transfer for fractional T1/PRI channels
– Transparent transmission/reception in frames delimited by 00
– Shared opening and closing flag
– Flag stuffing, flag detection, flag generation in the abort case
– Error detection (non octet frame content, short frame, long frame)
– Transparent transmission/reception with GSM 08.60 frame structure
– Automatic 0000
– Support of 40, 39
– Error detection (non octet frame contents, short frame, long frame)
– Channel inversion (data, flags, IDLE code)
– Format conventions as in CCITT Q.921 § 2.8
– Data over- and underflow detected
interframe-time-fill ‘1’s or flags
of short frames, non-octet frame content)
the synchronization pattern in transmit direction
during transmission; changes monitored and reported in receive direction
in the abort case with programmable flag
H
flag generation/detection
1
/
2
, 40
1
/
2
octet frames
9
H
flags
Introduction
PEB 20324
PEF 20324
04.99