pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 45

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

PEB 20324
PEF 20324
Electrical Characteristics
As a master the MUNICH128X reads/writes data from/to host memory using DMA and
burst. The slave mode is used by an CPU to access the MUNICH128X PCI Configuration
Space and the on-chip registers.
5.7.1.1
PCI Read Transaction
The transaction starts with an address phase which occurs during the first cycle when
FRAME is activated (clock 2 in figure 5-4). During this phase the bus master (initiator)
outputs a valid address on AD(31:0) and a valid bus command on C/BE(3:0). The first
clock of the first data phase is clock 3. During the data phase C/BE indicate which byte
lanes on AD(31:0) are involved in the current data phase.
The first data phase on a read transaction requires a turn-around cycle. In figure 5-4 the
address is valid on clock 2 and then the master stops driving AD. The target drives the
AD lines following the turnaround when DEVSEL is asserted. (TRDY cannot be driven
until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once
enabled, the AD output buffers of the target stay enabled through the end of the
transaction.
A data phase may consist of a data transfer and wait cycles. A data phase completes
when data is transferred, which occurs when both IRDY and TRDY are asserted. When
either is deasserted a wait cycle is inserted. In the example below, data is successfully
transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The
first data phase completes in the minimum time for a read transaction. The second data
phase is extended on clock 5 because TRDY is deasserted. The last data phase is
extended because IRDY is deasserted on clock 7.
The Master knows at clock 7 that the next data phase is the last. However, the master is
not ready to complete the last transfer, so IRDY is deasserted on clock 7, and FRAME
stays asserted. Only when IRDY is asserted can FRAME be deasserted, which occurs
on clock 8.
Hardware Reference Manual
45
04.99