pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 31

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

PEB 20324
PEF 20324
Functional Description
3.3.3.2
Rx Block
Receive Buffer (RB)
The Rx Block of the HDLC Controller contains a 1024 byte buffer (RB) which is allocated
to channels via requests from the protocol controller, as determined by the received data
for each channel.
HDLC Protocol
Flag detection (supports multiple flags between packets or a single flag shared as a
closing flag and an opening flag between packets), abort character detection, idle code
detection, zero-bit detection and deletion, packet length count, and CRC checking (either
16-bit or 32-bit) are performed.
V.110 and V.30 Protocol
Bit framing from 600 bit/s to 38.4 Kbit/s, automatic synchronization of the
synchronization pattern, detection of loss of synchronization, programmable E/SX bits
(including during run–time) are performed.
Transparent Mode A
Mode A supports slot synchronous transparent reception without frame structure. It
provides flag detection, flag extraction and synchronized data transfer for fractional T1/
E1 PRI applications.
Transparent Mode B
This mode supports transparent reception in frames delimited by 00
flags. Sharing
H
closing flag and opening flag, and flag detection.
Transparent Mode R
This mode supports transparent reception with GSM 08.60 frame structure with
automatic 0000
flag detection. Support of 40, 39.5, and 40.5 octet frames, and error
H
detection (non–octet frame contents, short frame, long frame).
Protocol Independence
Channel inversion (data, flags, idle code) follows the format conventions as in CCITT
Q.921, data overflow and underflow detection.
Hardware Reference Manual
31
04.99