pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 19

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

Table 2-3
Pin No.
96
94
95
90
92
91
93
Hardware Reference Manual
Symbol
RxCLK2
RxD2
RSP2
TxCLK2
TxD2
TSP2
TxDEN2
Pin Descriptions by Functional Block: Port 2 Serial Interface
I
Type Description
I
I
I
I
O
O
Receive Clock 2
The clock input pin used for sampling the data on
RxD2. The MUNICH128X supports the following PCM
clock rates, programmed via the MODE1 register:
T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz;
E1: 2.048 MHz, 4.096 MHz, 8.192 MHz.
Receive Data 2
The data input pin which is sampled using RxCLK2.
Receive Synchronization Pulse 2
The input pin used for Rx PCM frame synchronization;
the synchronization pulse marks the first bit in the
PCM frame.
Transmit Clock 2
The clock input used for clocking out the data on
TxD2. In most applications, the signal that drives this
pin is externally connected to RxCLK2.
Transmit Data 2
Provides the data which is clocked out of the
MUNICH128X by TxCLK2; data is push-pull for active
bits in the PCM frame and TRISTATE for inactive
bits.
Transmit Synchronization Pulse 2
The input pin used for Tx PCM frame synchronization;
the synchronization pulse marks the last bit in the
PCM frame.
Transmit Data Enable 2
An active low output signal which specifies data on the
TxD2 output pin is valid.
19
Pin Descriptions
PEB 20324
PEF 20324
04.99