pef20324 Infineon Technologies Corporation, pef20324 Datasheet - Page 47

• Manufacturer Part Number: pef20324
• Description: Multichannel Network Interface Controller With 128 Channels Extended
• Manufacturer: Infineon Technologies Corporation

5.7.1.2
The transaction starts when FRAME is activated (clock 2 in figure 5-5). A write
transaction is similar to a read transaction except no turnaround cycle is required
following the address phase. In the example, the first and second data phases complete
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clock 8).
Figure 5-5
Hardware Reference Manual
CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
PCI Write Transaction
1
PCI Write Transaction
Bus CMD
Address
Address
Phase
2
Data 1
BE’s-1
Phase
Data
3
Data 2
BE’s-2
Phase
Data
4
Bus Transaction
47
5
6
Phase
BE’s-3
Data
Electrical Characteristics
Data 3
7
8
PEB 20324
PEF 20324
ITD07576
9
04.99