m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 137

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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12. DMAC
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Figure 12.1 Register Mapping for DMAC
0
2
1
9
This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a
destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized when using
DMAC. DMAC2 and DMAC3 share registers required for high-speed interrupts. High-speed interrupts
cannot be used when using three or more DMAC channels.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU.
The cycle-steal method employed by DMAC enables high-speed operation between a transfer request and
the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 12.1 shows a mapping of registers to
be used for DMAC. Table 12.1 lists specifications of DMAC. Figures 12.2 to 12.5 show registers associ-
ated with DMAC.
Because the registers shown in Figure 12.1 are allocated to the CPU, use the LDC instruction to write to the
registers. To set DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register
bank 1) and set R0 to R3, A0, A1 registers with the MOV instruction.
To set DSA2 and DSA3 registers, set the B flag to "1" and set the SB, FB, SVP, VCT registers with the LDC
instruction. To set the DRA2 and DRA3 registers, set the SVP, VCT registers with the LDC instruction.
C
3 .
B
8 /
0
When Three or More DMAC Channels are Used,
the Register Bank 1 is Used as DMAC Registers
1
DMAC-Associated Registers
NOTES:
0
3
3
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1. Registers are used for repeat transter, not for single transfer.
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4
a
0 -
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3 .
1
DMA2 (A0)
DMA3 (A1)
DSA2 (SB)
DSA3 (FB)
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, 1
3
p
1
DSA0
DSA1
DRA0
DRA1
DMA0
DMA1
DCT2 (R0)
DCT3 (R1)
DRC2 (R2)
DRC3 (R3)
2
(
0
M
DCT0
DCT1
DRC0
DRC1
0
3
6
2
DMD0
DMD1
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Page 114
8 /
, 3
DMA2 Transfer Count Register
DMA2 Transfer Count Reload Register
DMA3 Memory Address Register
DMA3 SFR Address Register
DMA3 Transfer Count Register
DMA3 Transfer Count Reload Register
DMA2 Memory Address Register
DMA2 SFR Address Register
DMA 0 Transfer Count Register
DMA Mode Register 0
DMA Mode Register 1
DMA 1 Transfer Count Register
DMA 0 Transfer Count Reload Register
DMA 1 Transfer Count Reload Register
DMA 0 Memory Address Register
DMA 1 Memory Address Register
DMA 1 SFR Address Register
DMA 0 Memory Address Reload Register
DMA 1 Memory Address Reload Register
DMA 0 SFR Address Register
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3
2
C
f o
8 /
4
8
3
8
) T
(1)
(1)
(1)
(1)
(1)
(1)
When Three or More DMAC Channels are Used,
the High-Speed Interrupt Register is Used as DMAC
Registers
When using DMA2 and DMA3, use the CPU registers shown in parentheses ().
DRA2 (SVP)
DRA3 (VCT)
SVF
DMA2 Memory Address Reload Register
DMA3 Memory Address Reload Register
Flag Save Register
(1)
(1)
12. DMAC