m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 397

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
Figure 24.8 PS2 Register and PS3 Register
2
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
o r
n
Function Select Register A2
Function Select Register A3
b7
0 0
b7
3 .
1
u
NOTES:
, 1
3
p
b6
b6
1
2
(
1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
M
0
b5
b5
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the
instruction to set the PD9 register.
0
3
6
2
b4
0 0
b4
C
Page 374
8 /
b3
b3
, 3
b2
b2
M
b1
b1
3
2
b0
C
b0
f o
8 /
4
(b4 - b3)
(b7 - b6)
3
Symbol
PS2_0
PS2_1
PS2_2
Symbol
PS3_0
PS3_1
PS3_2
PS3_3
PS3_4
PS3_5
PS3_6
PS3_7
8
) T
(b5)
8
Bit
Bit
Symbol
PS2
Symbol
PS3
Port P8
Function Select Bit
Port P8
Function Select Bit
Port P8
Function Select Bit
Reserved Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved Bit
Port P9
Function Select Bit
Port P9
Function Select Bit
Port P9
Function Select Bit
Port P9
Function Select Bit
Port P9
Function Select Bit
Port P9
Function Select Bit
Port P9
Function Select Bit
Port P9
Function Select Bit
(1)
Bit Name
Bit Name
0
1
2
0
1
2
3
4
5
6
7
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Address
03B4
Address
03B5
16
16
Set to "0"
Set to "0"
0 : I/O port
1 : Selected by the PSL2_0 bit
0 : I/O port
1 : Selected by the PSL2_1 bit
0 : I/O port
1 : Selected by the PSL2_2 bit
0 : I/O port
1 : Selected by the PSL3_2 bit
0 : I/O port
1 : CLK4 output
0 : I/O port
1 : T
0 : I/O port
1 : CLK3 output
0 : I/O port
1 : Selected by the PSL3_1 bit
0 : I/O port
1 : RTS3
0 : I/O port
1 : RTS4
0 : I/O port
1 : Selected by the PSL3_7 bit
X
D4/SDA4 output
Function
After Reset
00X0 0000
After Reset
00
16
Function
2
24. Programmable I/O Port
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW