m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 254

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
. v
3
J
Figure 17.5 AD1CON0 Register
0
2
1
9
C
3 .
B
8 /
0
1
0
3
3
J
G
A/D1 Control Register 0
4
a
b7
0 -
n
o r
NOTES:
3 .
1
b6
u
1. When the AD1CON0 register is rewritten during the A/D conversion, the conversion result is
2. Set analog input pins again after changing A/D operation mode.
3. This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1.
4. The APS1 to APS0 bit in the AD1CON2 register select i=0, 2 or 15.
5. i=0 or 2 is available in single-chip mode only.
6. i=15 is available in the 144-pin package.
7. To set the TRG bit to "1", select the cause of trigger by setting the the TRG1 and TRG0 bits in the
8.
, 1
3
p
1
indeterminate.
AD1CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1".
b5
Combination of the CKS0 and CKS1 bits selects
2
(
0
M
AD
CKS0
AD
0
b4
0
0
1
1
3
6
frequency must be under 16 MHz when V
frequency must be under 10 MHz when V
2
b3
C
Page 231
8 /
b2
CKS1
, 3
0
1
0
1
b1
M
3
b0
2
f
f
f
C
f o
AD
AD
AD
8 /
Symbol
ADST
CKS0
4
MD0
MD1
TRG
CH0
CH1
CH2
divided by 4
divided by 3
divided by 2
Bit
3
8
Symbol
AD1CON0
8
) T
AD
f
AD
(1)
Analog Input Pin
Select Bit
A/D Operation
Mode Select Bit 0
Trigger Select Bit
A/D Conversion
Start Flag
Frequency Select
Bit
(8)
Bit Name
(2, 3, 4, 5, 6)
Address
01D6
CC
CC
AD
16
=5V.
=3.3V.
(2)
.
b2 b1
b4 b3
0 : Software trigger
1 : External trigger, hardware trigger
0 0 0 : ANi
0 0 1 : ANi
0 1 0 : ANi
0 1 1 : ANi
1 0 0 : ANi
1 0 1 : ANi
1 1 0 : ANi
1 1 1 : ANi
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or 1
0 : A/D conversion stops
1 : A/D conversion starts
0 : Select from f
1 : Select from f
b0
0
1
2
3
4
5
6
7
AD
AD
After Reset
00
Function
16
/3 or f
/1 or f
AD
AD
(7)
/4
/2
(i=0, 2, 15)
(7)
17. A/D Converter
RW
RW
RW
RW
RW
RW
RW
RW
RW