m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 76

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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7.1.1 Selecting External Address Bus
7.1.2 Selecting External Data Bus
7.1.3 Selecting Separate/Multiplexed Bus
1
9
C
3 .
B
The number of externally-output address bus, chip-select signals and chip-select-assigned address
space (CS area) varies depending on each external space mode. The PM11 to PM10 bits in the PM1
register determine the external space mode.
When using the DRAMC, row addresses and column addresses are multiplexed to output in the DRAM
area.
The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the
external space 3, after reset, becomes 16 bits wide when an "L" signal is applied to the BYTE pin and 8
bits wide when an "H" signal is applied. Do not change the BYTE pin level while the microcomputer is
operating. The internal bus is always 16 bits wide.
The PM05 to PM04 bits in the PM0 register determine either a separate or multiplexed bus as bus format .
8 /
0
1
7.1.3.1 Separate Bus
7.1.3.2 Multiplexed Bus
0
3
The separate bus is a bus format which allows the microcomputer to input and output data and ad-
dress using separate buses. The DS register selects 8-bit or 16-bit data bus as the external data bus
per external space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P
becomes the data bus and port P
"1" (16-bit data bus), ports P0 and P1 become the data bus. When the microcomputer accesses a
space while the DSi bit set to "0", port P1 is indeterminate.
If the microcomputer accesses a space with the separate bus, the WCR register determines the num-
ber of software wait states inserted.
The multiplexed bus is a bus format which allows the microcomputer to input and output data and
address via bus by timesharing. D
data bus. D
microcomputer accesses a space with the multiplexed bus, the WCR register can be set to either two
wait states or three wait states. Two-wait-state access is automatically selected if the WCR register is
set to no wait state or one wait state. Refer to 7.2.4 Bus Timing for details.
The microcomputer starts operation using the separate bus after reset. Therefore, the multiplexed bus
can be assigned to access the CS1 area, the CS2 area, or all CS areas. However, the multiplexed bus
cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits
in the PM0 register are set to "11
to A
3
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4
a
0 -
n
o r
3 .
15
1
_____
u
, 1
3
, of an address are output. See Table 7.2 for details.
p
1
2
(
0
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0
3
6
2
0
C
to D
8 /
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, 3
15
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are multiplexed with A
3
2
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8 /
4
8
3
8
) T
_______
2
1
_____
" (access all CS areas with the bus), only 16 low-order bits, from A
0
becomes the programmable I/O port. If one of the DSi bits is set to
to D
7
are multiplexed with A
0
_______
to A
_____
15
in space accessed by the 16-bit data bus. If the
_____
0
to A
7
in space accessed by the 8-bit
7. Bus
0
0