m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 299

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
2
0
Table 21.9 Single-phase Waveform Output Mode Specifications
Waveform Output Start Condition
Waveform Output Stop Condition
Interrupt Request
OUTCij Pin
Selectable Function
NOTES:
Output Waveform
1
21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3)
9
C
3 .
B
8 /
1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by
2. OUTC0
3. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed
Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) becomes high ("H") when the value of the base
timer matches that of the GiPOj register . The "H" signal switches to an "L" signal when the base timer
reaches "0000
signal is output when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the
waveform being output is inversed. See Figure 21.24 for details on single-phase waveform mode opera-
tion. Table 21.9 lists specifications of single-phase waveform mode.
0
1
3
0
(OUTC1
both time measurement function and waveform generation function
3
J
G
4
a
0 -
n
o r
3 .
1
u
(2)
, 1
3
p
0
Item
1
0
, OUTC0
2
(
to OUTC1
M
0
0
3
(3)
6
16
2
C
". If the IVL bit in the GiPOCRj register is set to "1" (outputs "H" as default value), an "H"
Page 276
8 /
1
, OUTC0
, 3
7
M
pins when using group 0 and group 1 cascaded connection)
3
2
C
(1)
f o
4
, OUTC0
8 /
4
3
8
The IFEj bit in the GiFE register is set to "1" (channel j function enabled)
• Free-running operation
• The base timer is reset by matching the base timer with the GiPO0 register
The IFEj bit is set to "0" (channel j function disabled)
The POijR bit in the interrupt request register is set to "1" (interrupt requested)
when the value of the base timer matches that of the GiPOj register. (See
Figure 10.14)
Pulse signal output pin
• Default value set function : Set starting waveform output level
• Inversed output function : Waveform output level is inversed and output from
• Cascaded connection function: Connect group 0 and group 1 to operate as a
) T
8
Cycle
(the RST2 to RST0 bits in the GiBCR1 (i=0 to 3) register are set to "000
"L" width
"H" width
(the RST1 bit is set to "1", and the RST0 and the RST2 bit are set to "0")
Cycle
"L" width
"H" width
the OUTCij pin
32-bit base timer
m : setting value of the GiPOj register (j=0 to 7), 0000
m : setting value of the GiPOj register (j=1 to 7), 0000
n : setting value of the GiPO0 register, 0001
If m
5
, OUTC1
n+2, the output level is fixed to "L"
0
:
:
:
:
:
:
to OUTC1
65536-m
65536
n+2-m
f
m
f
f
n+2
f
f
BTi
f
BTi
BTi
BTi
BTi
m
BTi
21. Intelligent I/O (Waveform Generation Function)
7
, OUTC2
Specification
0
to OUTC2
16
7
, and OUTC3
to FFFD
16
16
16
to FFFF
to FFFF
0
to OUTC3
16
16
2
")
7
pins