m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 230

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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Figure 16.23 Serial Bus Communication Control with SS Pin
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0
16.4.1 SSi Input Pin Function (i=0 to 4)
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When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the SSi input pin function is
selected, activating the pin function.
The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave.
When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting deter-
mines which master microcomputer is active and when.
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16.4.1.1 When Setting the DINC Bit to "1" (Slave Mode)
16.4.1.2 When Setting the DINC Bit to "0" (Master Mode)
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0
3
When an "H" signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a high-imped-
ance state and the transfer clock input to the CLKi pin is ignored. When a low-level signal ("L") is
applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled.
When an "H" signal is applied to the SSi pin, serial communication is available due to transmission
privilege. The master outputs the transfer clock. When an "L" signal is applied to the SSi pin, it indi-
cates that another master is active and TxDi, RxDi and CLKi pins are placed in a high-impedance
state. Moreover, a fault error occurs and the IR bit in the BCNiIC register is set to "1" (interrupt
requested). The ERR bit in the UiSMR3 register indicates whether a fault error occurs.
In master mode, software interrupt numbers 39, 40 and 41 are used for the fault error interrupt. The
fault error interrupt is generated when the ERR bit changes "0" to "1". The fault error interrupt of
UART0 and of UART3 share an interrupt vector. The fault error interrupt of UART1 and of UART4
share an interrupt vector. The IFSR6 and IFSR7 bits in the IFSR register determine which fault error
interrupt is used.
Communication is not terminated even if a fault error is generated while communicating. To stop
communication, the SMD 2 to SMD0 bit in the UiMR register is set to "000
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Microcomputer
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4
Master
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P9
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P9
P9
8
P9
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0(
2(
3(
RxD
CLK
TxD
SS
P1
P1
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3
3
3
3
2
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_____
_____
____
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P9
P9
P9
P9
P9
P9
P9
P9
3(
0(
2(
3(
0(
2(
Microcomputer
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Microcomputer
SS
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SRxD
SS
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SRxD
STxD
STxD
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3
Slave
Slave
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3
3
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3
3
3
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16. Serial I/O (Special Function)
2
" (serial I/O disabled).
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