r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1015

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

23.3
The H-UDI has the following registers.
Table 23.2 Register Configuration
23.3.1
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
23.3.2
SDIR is a 16-bit read-only register. It is initialized by TRST assertion or in the TAP test-logic-
reset state, and can be written to by the H-UDI irrespective of the CPU mode. Operation is not
guaranteed if a reserved command is set in this register. The initial value is H'EFFD.
Initial value:
Register Name
Bypass register
Instruction register
Note:
R/W:
Bit:
*
The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value.
Register Descriptions
Bypass Register (SDBPR)
Instruction Register (SDIR)
15
1*
R
14
1*
R
13
1*
R
SDIR
Abbreviation
SDBPR
12
0*
R
TI[7:0]
11
1*
R
10
1*
R
Section 23 High-Performance User Debugging Interface (H-UDI)
1*
R/W

R
R
9
1*
R
8
Initial Value

H'EFFD
R
7
1
-
R
6
1
-
Rev. 2.00 Dec. 09, 2005 Page 991 of 1152
R
5
1
-
Address

H'FFFE2000
R
4
1
-
R
3
1
-
R
2
1
-
REJ09B0191-0200
Access Size

16
R
1
0
-
R
0
1
-