r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 357
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r5s72060w200fpv
Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S72060W200FPV.pdf
(1180 pages)
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Section 8 Bus State Controller (BSC)
(1)
Basic Timing for Memory Card Interface
Figure 8.43 shows the basic timing of the PCMCIA IC memory card interface. When areas 5 and 6
are specified as the PCMCIA interface, the bus is accessed with the IC memory card interface
according to the SA[1:0] bit settings in CS5WCR and CS6WCR. If the external bus frequency
(CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable
signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) to the RD and WE signals
become insufficient. To prevent this error, this LSI enables the setup times and hold times for
areas 5 and 6 to be specified independently, using CS5WCR and CS6WCR. In the PCMCIA
interface, as in the normal space interface, a software wait or hardware wait using the WAIT pin
can be inserted. Figure 8.44 shows the PCMCIA memory bus wait timing.
Tpcm1
Tpcm1w
Tpcm1w
Tpcm1w
Tpcm2
CKIO
A25 to A0
CExx
RD/WR
RD
Read
D15 to D0
WE
Write
D15 to D0
BS
Figure 8.43 Basic Access Timing for PCMCIA Memory Card Interface
Rev. 2.00 Dec. 09, 2005 Page 333 of 1152
REJ09B0191-0200
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