r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 55

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
31 to 15 —
14
13
12 to 10 —
9
8
7 to 4
3, 2
1
0
(2)
(3)
interrupt.
(4)
TBR is referenced as the start address of a function table located in memory in a
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.
GBR is referenced as the base address in a GBR-referencing MOV instruction.
VBR is referenced as the branch destination base address in the event of an exception or an
Global Base Register (GBR)
Vector Base Register (VBR)
Jump Table Base Register (TBR)
Bit Name Initial Value
BO
CS
M
Q
I[3:0]
—
S
T
All 0
0
0
All 0
—
—
1111
All 0
—
—
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
BO Bit
Indicates that a register bank has overflowed.
CS Bit
Indicates that, in CLIP instruction execution, the value
has exceeded the saturation upper-limit value or
fallen below the saturation lower-limit value.
Reserved
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level
Reserved
These bits are always read as 0. The write value
should always be 0.
S Bit
Specifies a saturation operation for a MAC
instruction.
T Bit
True/false condition or carry/borrow bit
Rev. 2.00 Dec. 09, 2005 Page 31 of 1152
REJ09B0191-0200
Section 2 CPU