r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 84

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
Rev. 2.00 Dec. 09, 2005 Page 60 of 1152
REJ09B0191-0200
Instruction
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULR
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
SUBV
@Rm+,@Rn+
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,@Rn+
R0,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Instruction Code
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0100nnnn10000000
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Operation
Byte in Rm is
zero-extended → Rn
Word in Rm is
zero-extended → Rn
Signed operation of (Rn) ×
(Rm) + MAC → MAC
32 × 32 + 64 → 64 bits
Signed operation of (Rn) ×
(Rm) + MAC → MAC
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
R0 × Rn → Rn
32 × 32 → 32 bits
Signed operation of Rn × Rm
→ MACL
16 × 16 → 32 bits
Unsigned operation of Rn ×
Rm → MACL
16 × 16 → 32 bits
0-Rm → Rn
0-Rm-T → Rn, borrow → T
Rn-Rm → Rn
Rn-Rm-T → Rn, borrow → T
Rn-Rm → Rn, underflow → T
Execu-
tion
Cycles
1
1
4
3
2
2
1
1
1
1
1
1
1
T Bit








Borrow Yes

Borrow Yes
Over-
flow
SH2,
SH2E SH4 SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes