r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 233

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
8 to 6
5
4
Bit Name
DMAIW[2:0] 000
DMAIWA

Initial
Value
0
1
R/W
R/W
R/W
R
Method of inserting wait states between access cycles
Description
Wait states between access cycles when DMA single
address transfer is performed.
Specify the number of idle cycles to be inserted after
an access to an external device with DACK when DMA
single address transfer is performed. The method of
inserting idle cycles depends on the contents of
DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
when DMA single address transfer is performed.
Specifies the method of inserting the idle cycles
specified by the DMAIW[2:0] bit. Clearing this bit will
make this LSI insert the idle cycles when another
device, which includes this LSI, drives the data bus
after an external device with DACK drove it. However,
when the external device with DACK drives the data
bus continuously, idle cycles are not inserted. Setting
this bit will make this LSI insert the idle cycles after an
access to an external device with DACK, even when
the continuous access cycles to an external device
with DACK are performed.
0: Idle cycles inserted when another device drives the
1: Idle cycles always inserted after an access to an
Reserved
This bit is always read as 1. The write value should
always be 1.
data bus after an external device with DACK drove
it.
external device with DACK
Rev. 2.00 Dec. 09, 2005 Page 209 of 1152
Section 8 Bus State Controller (BSC)
REJ09B0191-0200