w925e625 ETC-unknow, w925e625 Datasheet - Page 15

• Manufacturer Part Number: w925e625
• Description: 8-bit Cid Microcontroller
• Manufacturer: ETC-unknow

TIMER CONTROL
TF1: Timer 1 overflows flag. This bit is set when Timer 1 overflows. It is cleared automatically when
TR1: Timer 1 runs control. This bit is set or cleared by software to turn timer on or off.
TF0: Timer 0 overflows flag. This bit is set when Timer 0 overflows. It is cleared automatically when
TR0: Timer 0 runs control. This bit is set or cleared by software to turn timer on or off.
IE1:
IT1:
IE0:
IT0:
TIMER MODE CONTROL
Bit7~4 control timer 1, bit3~0 control timer0
GATE: Gating control. When this bit is set, Timer x is enabled only while INTx pin is high and TRx
C/ T :
Note: X is either 0 or 1.
M1, M0: Mode Select bits:
M1
0
0
1
1
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise, it follows the pin.
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise, it follows the pin.
Interrupt 0 type control. Set/cleared by software to specify falling edge/ low level triggered
external inputs.
M0
control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
Timer or Counter Select. When cleared, the timer is incremented by internal clocks. When set,
the timer counts high-to-low edges of the Tx pin.
0
1
0
1
Mode
Mode 0: 13-bits timer
Mode 1: 16-bits timer
Mode 2: 8-bits with auto-reload from Thx
Reserved
Mnemonic: TCON
Mnemonic: TMOD
Bit:
Bit:
GATE
TF1
7
7
C/ T
TR1
6
6
TF0
M1
5
5
- 15 -
TR0
M0
4
4
GATE
Publication Release Date: July 4, 2005
IE1
3
3
Address: 88h
Address: 89h
(initial=00H)
(initial=00H)
C/ T
IT1
2
2
W925E/C625
IE0
M1
1
1
Revision A10
IT0
M0
0
0