w925e625 ETC-unknow, w925e625 Datasheet - Page 22

• Manufacturer Part Number: w925e625
• Description: 8-bit Cid Microcontroller
• Manufacturer: ETC-unknow

P3.7-0: P3 can be selected as input or output mode by the P3IO register, at initial reset, P3IO is set to
CID REGISTER
This SFR indicates the CID signal immediately. Register data is set or cleared by hardware only.
FCLK: FSK serial clock with the baud rate of 1200Hz.
FDATA: FSK serial bit data.
FCD: Set when FSK carrier is detected. Cleared when FSK carrier is disappeared.
DTMFD: Set when DTMF decoded data is ready. Cleared when DTMF signal ends.
FDR: Set when FSK 8 bits data is ready. Cleared before next FSK start bit comes
ALGO: Dual tone Alert signal Guard time detect signal. Set when a guard time qualified dual tone
RNG: Ring detection bit. High to indicate the detection of line reversal and/or ringing.
CID FLAG GENERATOR
FSF: Set when FSK Latch clock low to high. Cleared by software
DTMFDF: Set when DTMFD low to high. Cleared by software
FDRF: Set when FDR low to high. Cleared by software.
ALGOF: Set when ALGO low to high. Cleared by software.
RNGF: Set when RNG low to high. Cleared by software.
CID POWER CONTROL REGISTER
0FFH, P3 is used as input mode. When P3IO is set to 00h, the P3 is used as CMOS output
mode. Special function of P3 is described below.
alert signal has been detected. Cleared when the guard time qualified dual tone alert signal is
absent.
P3.5
P3.4
P3.3
P3.2
Mnemonic: CIDR
Mnemonic: CIDFG
Mnemonic: CIDPCR
Bit:
Bit:
Bit:
T1
T0
INT1
INT0
7
7
7
-
-
-
Timer/Counter 1 external count input
Timer/Counter 0 external count input
External interrupt 1
External interrupt 0
FCLK
6
6
6
-
-
FDATA
- 22 -
5
5
5
-
-
CIDE
FCD
FSF
4
4
4
DTMFDF FDRF
DTMFD
(initial=00H,read only)
(initial=00H)
(initial=00H)
3
3
3
-
Address: B2h
Address: B1h
Address: B3h
FSKE
FDR
2
2
2
W925E/C625
ALGOF
ALGO
CASE
1
1
1
DTMFE
RNGF
RNG
0
0
0