w925e625 ETC-unknow, w925e625 Datasheet - Page 38

• Manufacturer Part Number: w925e625
• Description: 8-bit Cid Microcontroller
• Manufacturer: ETC-unknow

mode and continues from there. When RGSL(PMR.5) bit is set to 1, the CPU will use the internal RC
oscillator instead of crystal to exit Power Down mode. The micro-controller will automatically switch
from RC oscillator to crystal after a warm-up delay of 65536 crystal clocks. The RC oscillator runs at
approximately 2 4 MHz. Using RC oscillator to exit from Power Down mode saves the time for waiting
crystal start-up. It is useful in the low power system which usually be awakened from a short operation
then returns to Power Down mode.
6.6
The user has several hardware related options for placing the W925E/C625 into reset condition. In
general, most register bits go to their reset value irrespective of the reset condition, but there are few
flags that initial states are dependant on the source of reset. User can recognize the cause of reset by
reading the flags. There are three ways of putting the device into reset state. They are External reset,
Power on reset and Watchdog reset.
External Reset
The device continuously samples the RESET pin at state C4 of every machine cycle. Therefore, the
RESET pin must be held for at least 2 machine cycles to ensure detection of a valid RESET low. The
reset circuitry then synchronously applies the internal reset signal. Thus, the reset is a synchronous
operation and requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RESET is 0. Even after RESET is
deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin
program execution from 0000h. There is no flag associated with the external reset condition. However,
since some flags indicate the cause of other two reset, the external reset can be considered as the
default reset if those two flags are cleared.
Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can reset
the watchdog timer at any time to avoid producing the flag WDIF. If the Watchdog reset is enabled and
the flag WDIF is set high, the watchdog timer reset is performed after the additional 512 clocks come.
This places the device into the reset condition. The reset condition is maintained by hardware for two
machine cycles. Once the reset is removed the device will begin execution from 0000h.
6.7
The W925E/C625 has a two priority levels interrupt structure with 11 interrupt sources. Each of the
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending
on bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode of the INT0 and the INT1 inputs are sampled in
every machine cycle. If the sample is high in one cycle and low in the next, then a high to low
transition is detected and the interrupts request flag Iex in TCON is set. The flag bit requests the
interrupt. Since the external interrupts are sampled every machine cycle, they have to be held high or
low for at least one complete machine cycle. The Iex flag is automatically cleared when the service
routine is called. If the level triggered mode is selected, then the requesting source has to hold the pin
low until the interrupt is serviced. The Iex flag will not be cleared by the hardware on entering the
Reset
Interrupt
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W925E/C625