w925e625 ETC-unknow, w925e625 Datasheet - Page 67

• Manufacturer Part Number: w925e625
• Description: 8-bit Cid Microcontroller
• Manufacturer: ETC-unknow

Notes:
1. The CPE designer may choose to set FSKE always high while the CPE is on-hook and the FSK signal is expected.
2. TW/P & E/312 specifies that the AC and DC loads should be applied between 250 – 400 Ms after the end of the ring
3. TW/P & E/312 specifies that the AC and DC loads should be removed between 50 – 150 ms after the end of the FSK
4. The CID may not be enable up at the first ring cycle after the FSK data had been processed.
TE DC load
TE AC load
burst.
signal.
RNG
CIDF
FSKE
A/B Wires
CIDE
FDATA
FCLK
FCD
FDR
Figure 6-31 Input and Output Timing of CCA Caller Display Service Data Transmission
Ring Burst
Note 1
Line Reversal
A
250 - 400 ms
B
Note 2
Ch. Seizure
...101010...
C
...
...
Mark
D
- 67 -
50 - 150 ms
Message
Data
E
...
...
Note 3
F
Publication Release Date: July 4, 2005
A = 200 - 450mS
B >= 500mS
C = 80 - 262mS
D = 45 - 262mS
E <= 2.5sec (500ms typical)
F >= 200mS
Note 4
First Ring Cycle
W925E/C625
Revision A10