w925e625 ETC-unknow, w925e625 Datasheet - Page 41

• Manufacturer Part Number: w925e625
• Description: 8-bit Cid Microcontroller
• Manufacturer: ETC-unknow

6.8
The W925E/C625 has 2 16-bit timer/counters. There are two 8-bit registers to perform a 16-bit
counting register in every timer/counter. In timer/counter 0, TH0 is the upper 8 bits register and TL0 is
the lower 8 bits register. Similarly timer/counter 1 have two 8-bit registers, TH1 and TL1. Each
timer/counter has 4 kind of clock sources which are Fosc/4, Fosc/64, Fosc/1024 and Fs. There are 3
operating modes in each timer/counter 0 and 1. The operating modes of timer/ counter0 is identical to
timer/counter1. The overflow signal of each timer/counter is sampled at phase 2 in every system
machine cycle, therefore when the system clock and the timer/counter clock both are from sub-
oscillator, if the overflow frequency is higher than Fs/4 the overflow flag can not be sampled correctly.
Only one overflow flag can be sampled in a machine cycle others will be missed.
MODE 0
In Mode 0, the timer/counters act as 13-bit timer/counters. The 13 bits consist of 8 bits of THx and
lower 5 bits of TLx. The upper 3 bits of TLx are ignored.
The negative edge of the clock causes the content of the TLx register to increase one. When the fifth
bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the count in THx
moves from FFh to 00h, then the overflow flag TFx is set. The counted input is enabled only if TRx is
set and either GATE=0 or INTx =1. When C/ T is set to 0, then it will count clock cycles, and if C/ T
is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1. When
the 13-bit count reaches 1FFFh, the next count will cause it to rollover to 0000h. The timer overflow
flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when they are
used as a timer, the bits of the CKCON1 select the time-base.
MODE1
Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a 13
bit counter.
(GATE = TMOD.7)
Programmable Timers/Counters
(TR1 = TCON.6)
GATE = TMOD.3
TR0 = TCON.4
(T1 = P3.5)
(INT1 = P3.3)
T0 = P3.4
INT0 = P3.2
PS: Functions of timer1 are shown in brackets
Fosc/1024
Fosc/64
Fosc/4
TM0=CKCON1.2, CKCON1.3
(TM1=CKCON1.4, CKCON1.5)
Fs
00
01
10
11
mux
Figure 6-5 Mode 0 & Mode 1 of Timer/Counter 0 & 1
(C/T = TMOD.6)
C/T = TMOD.2
0
1
- 41 -
0
(TL1)
TL0
4
(M1,M0 = TMOD.5,TMOD.4)
M1,M0 = TMOD.1,TMOD.0
Publication Release Date: July 4, 2005
7
(TF1)
TFx
TF0
00
01
0
W925E/C625
Interrupt
(TH1)
TH0
Revision A10
7