w925e625 ETC-unknow, w925e625 Datasheet - Page 27

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w925e625

Manufacturer Part Number
w925e625
Description
8-bit Cid Microcontroller
Manufacturer
ETC-unknow
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
w925e625FG
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
SERIAL DATA BUFFER 1
SBUF1.7-0: Serial data on the serial port 1 is read from or written to this location. It actually consists of
REGULATOR VOLTAGE CONTROL REGISTER
REGVC.3-0: 4 bits to tune the regulator output voltage.
POWER MANAGEMENT REGISTER
XT/ RG :Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system clock
RGMD: RC Mode Status. This bit indicates the current clock source of micro-controller. When cleared,
RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power Down
X2OFF: Set to disable sub-oscillator (32KHz oscillator)
X1OFF: Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit can
Note: The bit0 of this SFR must be set to 1.
Bit:
Bit:
Bit:
source. Clearing this bit selects the on-chip RC oscillator as clock source. X1UP (STATUS.4)
must be set to 1 and X1OFF (PMR.3) must be cleared before this bit can be set. Attempts to
set this bit without obeying these conditions will be ignored.
Mode. Setting this bit allows device operating from RC oscillator when a resume from Power
Down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator
has warmed-up following a resume from Power Down Mode.
only be set to 1 while the micro-controller is operating from the RC oscillator. Clearing this bit
restarts the crystal oscillator, the X1UP (STATUS.4) bit will be set after crystal oscillator
warmed-up has completed.
CPU is operating from the external crystal or oscillator. When set, CPU is operating from the
on-chip RC oscillator.
two separate internal 8-bit registers. One is the receive register, and the other is the
transmit buffer. Any read access gets data from the receive data buffer, while write
access is to the transmit data buffer.
XT/ RG
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
Mnemonic: SBUF1
Mnemonic: REGVC
Mnemonic: PMR
7
7
7
-
RGMD
6
6
6
-
RGSL
5
5
5
-
X2OFF
- 27 -
4
4
4
-
REGVC.3 REGVC.2 REGVC.1 REGVC.0
X1OFF
3
3
3
Publication Release Date: July 4, 2005
Address: C1h
Address: C2h
Address: C4h
(initial=00H) Read Only
(initial=00H)
(initial=81H)
2
-
2
2
W925E/C625
1
1
1
-
Revision A10
0
0
0
-

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