w925e625 ETC-unknow, w925e625 Datasheet - Page 39

• Manufacturer Part Number: w925e625
• Description: 8-bit Cid Microcontroller
• Manufacturer: ETC-unknow

W925E/C625
service routine. If the interrupt continues to be held low even after the service routine is completed,
then the processor may acknowledge another interrupt request from the same source. Note that the
external interrupts INT2 to INT3 are edge triggered only.
The TF0, TF1 flags generate the Timer 0, 1 Interrupts. These flags are set by the overflow in the Timer
0, Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the timer interrupt
is serviced.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-
out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the enable bit EIE.5
enables the interrupt, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are one interrupt sources
from the Serial block, which are obtained by SF1 in the SCON1. SF1 is cleared automatically when
the serial port interrupt is serviced.
The divider interrupt is generated by DIVF that is set when divider overflows. DIVF is set by hardware
and cleared when divider interrupt is serviced. The divider interrupt is enable/disable if the bit EDIV is
high/low.
The comparator interrupt is produced by COMPF, which is set when the RESC bit is changed from low
to high. RESC, which is the real-time result of comparator, set when the voltage of reference input is
higher than the voltage of analog input.
The CID interrupt is generated by CIDF. The CIDF is a logic OR output of all CID flags which are set
by hardware and cleared by software. The structure of the CID flags is shown in Figure 6-4.
Each of the individual interrupts can be enabled or disabled by setting or clearing the corresponding
bits in the IE and EIE SFR. A bit EA, which is located in IE.7, is a global control bit to enable/disable
the all interrupt. When bit EA is zero all interrupts are disable and when bit EA is high each interrupt is
enable individually by the corresponding bit.
RNGF
CIDF
FDRF
D
ALGOF
DTMFDF
FSF
System clock
R
Clear by software
Figure 6-4 The Structure of CID Flags
Priority Level Structure
There are two priority levels for the interrupts, high and low. The interrupt sources can be individually
set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower
priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts themselves.
This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests
having the same priority level. This hierarchy is defined as shown below; the interrupts are numbered
starting from the highest priority to the lowest.
Publication Release Date: July 4, 2005
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Revision A10