w925e625 ETC-unknow, w925e625 Datasheet - Page 44

• Manufacturer Part Number: w925e625
• Description: 8-bit Cid Microcontroller
• Manufacturer: ETC-unknow

The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a
known state. The RWT bit is used to restart the watchdog timer. This bit is self clearing, i.e. after
writing a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock
cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and CKCON.6).
When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the
time-out has occurred, the watchdog timer waits for an additional 512 clock cycles. The software must
issue a RWT to reset the watchdog before the 512 clocks have elapsed. If the Watchdog Reset EWT
(WDCON.1) is enabled, then 512 clocks after the time-out, if there is no RWT, a system reset due to
Watchdog timer will occur. This will last for two machine cycles, and the Watchdog timer reset flag
WTRF (WDCON.2) will be set. This indicates to the software that the watchdog was the cause of the
reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a
time-out and the RWT allows software to restart the timer. The Watchdog timer can also be used as a
very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an
interrupt will occur if the global interrupt enable EA is set.
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into
a known state.
The control bits that support the Watchdog timer are discussed below.
WATCHDOG CONTROL
WDIF: WDCON.3 – Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
WTRF: WDCON.2 – Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
EWT: WDCON.1 – Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog
WD1
0
0
1
1
watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur (if the
global interrupt enable is set and other interrupt requirements are met). Software or any reset
can clear this bit.
manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by
the watchdog timer.
timer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will
leave the timer running
This bit is useful for determined the cause of a reset. Software must read it, and clear it
WD0
0
1
0
1
WATCHDOG
INTERVAL
2
2
2
2
Table 6 Time-out values for the Watchdog timer
12
15
18
21
NUMBER OF
CLOCKS
2097152
262144
32786
4096
- 44 -
3.579545 MHZ
585.87 Ms
73.23 Ms
1.14 Ms
9.15 Ms
FOSC=
32768 HZ
0.125 S
FOSC=
64 S
1 S
8 S
W925E/C625
RESET OF
CLOCKS
2097664
262656
33280
4608