cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 150

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

8.2.8.1
CX28500 needs to send more data toward the TSIU for an in-progress transmit message, but the internal channel
FIFO is empty.
Reasons:
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Effects:
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Channel Level Recovery Actions:
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8.2.8.2
The TSYNC or STB input signal transitions from low to high, but at an unexpected time in comparison to the
internal frame synchronization flywheel mechanism. COFA errors are only applicable to channelized ports (i.e.,
unchannelized ports ignore the TSYNC input). Frame synchronization indicates the expected location of the first bit
of time slot 0 on the transmit serial data output. Lacking frame synchronization, the transmitter cannot map or align
time slots. This error affects all active channels on the respective port.
Reason:
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Effects:
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28500-DSH-002-C
Degradation of the Host subsystem or application software.
Buffer descriptor containing the continuation of a message is Host-owned.
PCI bus congestion.
TxBUFF Interrupt (if BUFFIEN = 1 in
Transmit channel enters deactivate state where the TSLP transmits a repetitive abort sequence of 16
consecutive 1s.
TDMA may read more buffers to refill the internal channel FIFO (since this process is asynchronous to the
TSLP), but eventually the TDMA stops servicing this channel since the TSLP has stopped sending data.
Transmit output is all 1s, or an ABORT code, to indicate a termination event.
Transmit channel complete reactivation is required.
Signal failure, glitch or realignment caused by the physical interface sourcing the TSYNC/STB input signal.
Causes serial interface to enter COFA condition until a TSYNC/STB pulse arrives and is followed by at least
the assigned number of time slots for this port, without another unexpected TSYNC/STB pulse.
For every active channel on the respective port, TSLP places channels into the deactivate state. Wherein,
TSLP sends a repetitive abort sequence of 16 consecutive ones.
Transmit COFA Interrupt (if COFAIEN = 1 in
NOTE:
NOTE:
Transmit Underrun [BUFF]
Transmit Change Of Frame Alignment (COFA)
Since CX28500 completely separates the two processes of loading data from the Host and
transmitting data to the serial interface, it is irrelevant to CX28500 how the underrun
condition was created. To be specific, there is no distinction between a BUFF error created
due to a Host-owned buffer descriptor or due to a latency-induced empty FIFO condition.
CX28500 behavior when encountering a buffer descriptor owned by the Host is described in
Table 6-40, Transmit Buffer
presence or absence of an underrun condition. The effects of an underrun condition, once
detected, are as described above, regardless of current buffer ownership.
COFA interrupt is generated immediately. To synchronize the Host’s response to a COFA
condition, a COFA Recovery interrupt is also provided.
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Section
Section
6.7.2).
Descriptor. The behavior is the same regardless of the
6.7.5).
®
Basic Operations
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