cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 49

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 1-8.
28500-DSH-002-C
Pin Label
RBS [4:0]
DEVSEL*
ACK64*
STOP*
TRDY*
SERR*
PERR*
IRDY*
IDSEL
INTA*
REQ*
GNT*
CX28500 Hardware Signal Definitions (6 of 7)
PCI Initialization Device
PCI Read Burst Size
Acknowledge 64-bit
PCI Initiator Ready
PCI Device Select
PCI Target Ready
PCI Bus Request
Signal Name
PCI Bus Grant
PCI CX28500
System Error
Parity Error
PCI Stop
Interrupt
Transfer
Select
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s/t/s I/
s/t/s I/
s/t/s I/
s/t/s I/
s/t/s I/
s/t/s I/
o/d O
o/d O
t/s O
t/s 0
I/O
O
O
O
O
O
O
I
I
ACK64* asserted indicates the selected target is ready to perform a 64-
bit transaction.
STOP* asserted indicates the selected target is requesting the master to
stop the current transaction.
IRDY* asserted indicates the current master’s readiness to complete the
current data phase.
TRDY* asserted indicates the target’s readiness to complete the current
data phase.
When asserted, DEVSEL* indicates that the driving device has decoded
its address as the target of the current cycle.
This input is used to select CX28500 as the target for configuration read
or write cycles.
Any PCI device can assert SERR* to indicate a parity error on the address
cycle or parity error on the data cycle of a special cycle command or any
other system error where the result will be catastrophic. CX28500 will
assert SERR* if it detects a parity error on the address cycle or
encounters an abort condition while operating as a PCI master.
Since SERR* is not an s/t/s signal, restoring it to the deasserted state is
done with a weak pullup (same value as used for s/t/s).
Note that CX28500 does not input SERR*. It is assumed that the Host
will reset CX28500 in the case of a catastrophic system error.
PERR* is asserted by the agent receiving data when it detects a parity
error on a data phase. It is asserted one clock after PAR is driven, which
is two clocks after the AD and CBE* parity was checked.
If CX28500 masters a PCI write cycle and—after supplying the data
during the data phase of the cycle—detects this signal being asserted by
the agent receiving the data, then CX28500 generates a PERR interrupt.
If CX28500 masters a PCI read cycle and—after receiving the data during
the data phase of the cycle—calculates that a parity error has occurred,
CX28500 asserts this signal and also generates the PERR Interrupt
Descriptor towards the Host.
INTA* is driven by CX28500 to indicate a CX28500 Layer 2 interrupt
condition to the Host processor.
CX28500 drives REQ* to notify the PCI arbiter that it desires to master
the bus. Every master in the system has its own REQ*.
The PCI bus arbiter asserts GNT* when CX28500 is free to take control of
the bus, assert FRAME*, and execute a bus cycle. Every master in the
system has its own GNT*.
Reports the number of dwords CX28500 attempts to read during its
subsequent master burst read transaction. These lines are driven only
during address phase of the master read transaction, where a value of
00000 means one-dword and a value of 11111 means 32 dwords.
®
Definition
Introduction
34