cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 168

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 10-6.
Table 10-7.
Table 10-8.
28500-DSH-002-C
FOOTNOTE:
(1)
(2)
(3)
(4)
(5)
FOOTNOTE:
(1)
(2)
T
Minimum and maximum times are evaluated at 80 pF equivalent load. Actual test capacitance may vary, and results should be correlated
to these specifications.
REQ* and GNT* are the only point-to-point signals, and have different output valid delay and input setup times than do bused signals.
GNT* has a setup of 10 ns; REQ* has a setup of 12 ns for 33 MHz.
For purposes of active/float timing measurements, the hi-Z or off state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification at 80 pF equivalent load.
Actual measurements were done with 0.5 ns for test equipment guardband.
The only open-drain outputs in the PCI interface are the INTA# signal and the SERR# signal.
The input test is done with 0.1 VDD_c of overdrive (over V
Production testing can use different voltage values, but must correlate results back to these parameters.
V
voltage values, but must correlate results back to these parameters.
Symbol
T
Symbol
T
T
val
T
val
max
su
rst_clk
T
rst-off
T
T
T
T
T
T
T
rrsu
rst
rrh
(o.d.)
val
off
(ptp)
(ptp)
on
ds
dh
Symbol
specifies the maximum peak-to-peak voltage waveform allowed for measuring input timing. Production testing can use different
V
V
V
—
V
max
test
th
tl
PCI Reset Parameters
PCI Input/Output Timing Parameters
PCI I/O Measure Conditions
Reset Active Time after Power Stable
Reset Active Time after Clock Stable
Reset Active to Float Delay
REQ64 to RST setup time
RST to REQ64 hold time
PCLK to Signal Valid Delay–Bused Signal
PCLK to Signal Valid Delay–Point To Point
PCLK to Signal Valid Delay–Open Drain
Float to Active Delay
Active to Float Delay
Input Setup Time to Clock–Bused Signal
Input Setup Time to Clock–Point To Point
Input Hold Time from Clock
Voltage Threshold High
Voltage Threshold Low
Voltage Test Point
Maximum Peak-to-Peak
Input Signal Edge Rate
(3)
(3)
Parameter
Parameter
Mindspeed Proprietary and Confidential
Mindspeed Technologies
(1)
(1)
Parameter
(
2)
(
5)
(2)
(
(2)
1, 2)
(
1, 2)
ih
and V
il
). Timing parameters must be met with no more overdrive than this.
10 T
Min
100
—
1
0
®
Electrical and Mechanical Specification
cyc
33 MHz
10, 12
Min
0
—
2
2
2
2
7
(4)
0.6 VDD_c
0.2 VDD_c
0.4 VDD_c
0.4 VDD_c
Value
33 MHz
Max
1
11
12
11
—
28
—
—
—
Max
—
—
40
—
50
66 MHz
Min
0
—
2
2
2
2
4
5
(4)
66 MHz
Max
10
10
10
—
14
—
—
—
Unit
V/ns
V
V
V
V
Units
ms
µs
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
153