cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 33

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cx28500

Manufacturer Part Number
cx28500
Description
Cx28500 Multichannel Synchronous Communications Controller
Manufacturer
Mindspeed Technologies
Datasheet

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The frame structure is designed to transport the unchannelized STS-1 Synchronous Payload Envelope (SPE).
The frame structure is designed to transport the unchannelized DS3 payload.
The frame structure is designed to transport 16 E1 signals that are mapped to and from E3.
1.9
Figure 1-8
Figure 1-8.
The following is a description of the block diagram.
28500-DSH-002-C
VC-11s and VC-12s extracted from mixed TUG-2s via the SDH framers
Host Interface (PCI): This block provides the communication path between the Host and CX28500.
Expansion Bus (EBUS): The EBUS is an extension of the Host Interface, which provides the Host with access
to control other devices on the local PC board.
Serial Interface Unit (SIU): This block provides the interface between 32 serial ports and the Receive and
Transmit Serial Line Processors block. A temporal buffering space is provided by SIU that is 48 bits per port,
PAR, PAR64
CBE[7:0]*
DEVSEL*
AD[63:0]
FRAME*
REQ64*
ACK64*
PRST_
PERR*
SERR*
TRDY*
STOP*
IDSEL
IRDY*
PCLK
REQ*
GNT*
INTA*
illustrates the CX28500 conceptual block diagram.
CX28500 Top Level Block Diagram
Block Diagram
64
2
8
Data
32 4
Interface
HOST
(PCI)
EBUS
CTRL
Stream
Stream
Data
Data
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RxDMA
TxDMA
and
Dwords
Dwords
Data
Data
JTAG
Processor
Processor
Rx Line
Tx Line
RSLP
TSLP
Stream
Stream
Data
Data
®
8
8
Interface
Access
Serial
(SIU)
Unit
Test
1
1
6
6
3
RCLK0,
TCLK0,
RSYNC0 (RSTUFF0),
TSYNC0 (TSTUFF0)
RDAT0,
ROOF0/CTS0(TSTB0),
TDAT0
RCLK31,
TCLK31,
RSYNC31 (RSTUFF31),
TSYNC31(TSTUFF31),
RDAT31,
ROOF31/CTS31(TSTB31),
TDAT31
Test Mode
Serial Port 31
Serial Port 0
Introduction
500052_001
18

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