cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 183

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

A.3
•
•
•
•
•
•
•
•
•
A.4
Each PCI transaction is accompanied by an associated overhead. The two types of PCI transaction and their
associated overheads are outlined below.
A.4.1
A read transaction of X dwords of data including a Host access latency of r cycles takes (3 + X + r) cycles for a 32-
bit mode PCI or (3 + [(X/2)] + r) cycles for a 64-bit mode PCI. These include an address cycle and two bus
turnaround cycles.
A.4.2
A write transaction of X dwords of data, including a Host access latency of w cycles, takes (2 + X + w) cycles for a
32 bit mode PCI or (2 + [(X/2)] + w) cycles for a 64-bit mode PCI. These include one address cycle and one bus
turnaround cycle.
28500-DSH-002-C
Each servicing of a channel is initiated by its channel number reaching the front of the Service Queue and is
terminated after precisely one PCI transaction regardless of whether that transaction moves data or buffer
descriptor overhead. If a channel requires further servicing, the DMA Controller automatically replaces its
request at the back of the Service Queue.
The DMA Aging-Period is not relevant to PCI latency when considering the worst case scenario.
An internal, fairly weighted, round-robin scheme is used to decide whether the next PCI transaction is receive-
based or transmit-based.
Regardless of whether the PCI bus works in 32-bit or 64-bit mode, MaxData has a maximum value of 32
dwords (to limit the time of any one data transaction).
The PCI clock frequency is either 33 or 66 MHz.
The Host causes no bottleneck in the operation of CX28500 and Host access latency (TRDY delay) is
considered to be zero. Hence, this model also assumes that no PCI read transaction is ever retried due to
target unavailability and the PCI bridge FIFO is large enough to accept continuous CX28500 transactions
without becoming full.
An unchannelized port is considered for the purpose of calculations to be one channel. For the case of a
TSBUS interface, each Virtual Serial Port (VSP) is considered to be one channel.
Each packet is contained in one buffer in the Host memory. If this is not the case, extra overhead per packet is
associated with buffer descriptor management.
Interrupt service is not taken into consideration since using status for every BD is more demanding on the PCI.
NOTE:
NOTE:
Assumptions/Modes of Operation
PCI Transaction Timing
Read
Write
With usage of the fast back-to-back feature of the PCI, the number of turn around cycles
can be reduced. However in the following calculations the worst case has been considered
so the maximum number of cycles has been used.
With usage of the fast back-to-back feature of the PCI, the number of turn around cycles
can be reduced. However in the following calculations the worst case has been considered
so the maximum number of cycles has been used.
Mindspeed Proprietary and Confidential
Mindspeed Technologies
CX28500 PCI Bus Latency and Utilization Analysis
®
168