cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 48

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 1-8.
28500-DSH-002-C
Pin Label
CBE[7:0]*
AD[63:0]
FRAME*
REQ64*
PRST*
PAR64
PCLK
PAR
CX28500 Hardware Signal Definitions (5 of 7)
Request 64-bit Transfer
and Byte Enables
PCI MSB parity
Signal Name
PCI Command
PCI Address
PCI Frame
PCI Clock
PCI Reset
PCI Parity
and Data
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Mindspeed Technologies
s/t/s I/
t/s I/O AD[63:0] is a multiplexed address/data bus. A PCI transaction consists of
t/s I/O During the address phase, CBE[3:0]* contain command information
t/s I/O The number of 1s on PAR, AD[31:0], and CBE[3:0]* is an even number.
t/s I/O Same as PAR for CBE[7:4]* and AD[63:32].
t/s I/O CX28500 asserts this signal when it needs to perform a 64-bit transfer.
I/O
O
I
I
an address phase during the first clock period followed by one or more
data phases. AD[7:0] is the LSB. As a master, CX28500 supports both
32- and 64-bit operations. As a target, it supports only 32-bit operations.
PCLK provides timing for all PCI transitions. All PCI signals except
PRST*, INTA*, and INTB* are synchronous to PCLK and are sampled on
the rising edge of PCLK. CX28500 supports a PCI clock up to 66 MHz.
This input resets all functions on CX28500.
while CBE[7:4]* are unused; during the data phases, CBE[7:0]* contain
information denoting which byte lanes are valid.
PCI commands are defined as follows:
Note that the CX28500 does not accept target (slave) transactions if the
CBE bits are not all 0 (zeroes). Such transactions successfully complete
on the PCI bus, but are silently ignored by the CX28500 device. The CBE
bits function normally during all other times.
PAR always lags AD[31:0] and CBE* by one clock. During address
phases, PAR is stable and valid one clock after the address; during the
data phases it is stable and valid one clock after TRDY* on reads and one
clock after IRDY* on writes. It remains valid until one clock after the
completion of the data phase.
FRAME* is driven by the current master to indicate the beginning and
duration of a bus cycle. Data cycles continue as FRAME* stays asserted.
The final data cycle is indicated by the deassertion of FRAME*. For a non-
burst, one-data-cycle bus cycle, this pin is only asserted for the address
phase.
This signal is used during PCI reset to inform the system that the PCI is
64-bits wide.
Oh
Dh
1h
6h
7h
Ah
Bh
Ch
Eh
Fh
CBE[3:0]
®
0000b
0001b
0110b
0111b
1010b
1011b
1100b
1101b
1110b
1111b
Memory Write and Invalidate
Definition
Interrupt Acknowledge
Memory Read Multiple
Configuration Write
Configuration Read
Dual Address Cycle
Memory Read Line
Command Type
Memory Write
Memory Read
Special Cycle
Introduction
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