cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 187

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

A.11
The filling of an SLP buffer can be divided into 3 sections:
1. Up to the point where the amount of data crosses the threshold;
2. The amount of data filled in max L
3. The amount of time left to fill the rest of the buffer.
Diagrammatically:
•
•
•
In the case of the receive direction, the amount of time that an SLP internal buffer takes to fill the Spare space in
the buffer is the Maximum Tolerable Delay. This time period is usable by the Host (or other component) once per
number of extra cycles it takes to completely empty the amount of data filled in that time. Hence if the channel
buffer is exactly in data equilibrium, this spare can only be used once until the same amount of cycles has been
returned to CX28500.
In the case of the transmit direction, the amount of time that an SLP internal buffer takes to empty the Spare space
in the buffer is the Maximum Tolerable Delay. This time period is usable by the Host (or other component) once per
number of extra cycles it takes to completely fill the amount of data emptied in that time. Hence if the channel buffer
is exactly in data equilibrium, this spare can only be used once until the same amount of cycles has been
“returned” to CX28500.
The value of the Maximum Tolerable Delay can be calculated and is represented by the following equation:
A.12
1. An overflow occurs if one of the following is false:
2. PCI bus utilization allows an estimation of the number of CX28500 devices that can share one PCI bus.
3. The amount of data filled during the usage of spare cycles plus the amount of data already in the buffer can be
28500-DSH-002-C
Spare
Amount filled in max L
Threshold Data
a. Utilization <1;
b. L
c. Amount of data transferred > Amount of data transferred in/out of the PCI during L
However, the relationship between utilization and the number of CX28500 devices is not linear.
used as the figure for the maximum allowable threshold.
same time
pci
< L
ch
NOTE:
;
Maximum Tolerable Delay
Other Considerations
pci
To avoid overflow or underflow of an internal SLP buffer, U must be less than one and
Maximum Feasible PCI Latency of each channel must be less than the Maximum Endurable
Latency of that channel.
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pci
U
;
=
NumCh
∑
max L
(
Y
bit rx
ch
–
CX28500 PCI Bus Latency and Utilization Analysis
–
•
max L
f
ch rx
–
pci
+
Y
®
bit tx
–
•
f
ch tx
–
)
pci
CX28500 during the
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