cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 172

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

10.2.4
Figure 10-7. EBUS Write/Read Cycle, Intel-Style
28500-DSH-002-C
GENERAL NOTE:
1. HLDA assertion depends on the external bus arbiter. While HOLD and HLDA are both deasserted, MUSYCC
2. One ECLK cycle after HLDA assertion, MUSYCC outputs valid command bus signals: EBE, ALE, RD*,
3. Two ECLK cycles after HLDA assertion, MUSYCC outputs valid EAD address signals.
4. ALE assertion occurs 3 ECLK cycles after HOLD and HLDA are both asserted. ALAPSE inserts a variable
5. EAD address remains valid for one ECLK cycle after ALE falling edge. During a write transaction, MUSYCC
6. ELAPSE inserts a variable number of ECLK cycles to extend RD*/WR* low pulse width and EAD data
7. EAD write data and EBE byte enables remain valid for one ECLK cycle after RD*/WR* deassertion.
8. One ECLK after RD* or WR* deassertion, HOLD is deasserted and the bus is parked (command bus
9. Command bus is unparked (three-stated) one ECLK after HLDA deassertion; two different unpark phases
10. BLAPSE inserts a variable number of ECLK cycles to extend HOLD deassertion interval until the next bus
11. The address line A31 must be asserted in all transactions.
places shared EBUS signals in high impedance (three-state, shown as dashed lines).
and WR*.
number of ECLK cycles to extend ALE high pulse width and EAD address interval.
outputs valid EAD write data one ECLK prior to WR* assertion. During a read transaction, EAD data lines
are inputs.
intervals. Read data inputs are sampled on ECLK rising edge coincident with RD* deassertion.
deasserted, EAD three-state). The bus parked state ends when HLDA is deasserted.
are shown, indicating the dependence on HLDA deassertion. If HLDA remained asserted until the next bus
request, then command bus remains parked until one ECLK cycle following the next HOLD assertion.
Caution: Whenever HLDA is deasserted, all shared EBUS signals are forced to three-state after one ECLK
cycle, regardless of whether the EBUS transaction was completed. MUSYCC does not reissue or repeat
such an aborted transaction.
request.
EBUS Arbitration Timing Specification
WR* (write)
WR* (read)
RD* (write)
RD* (read)
See Notes
EAD[31:0]
EBE[3:0]*
HOLD
HLDA
ECLK
ALE
1
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Mindspeed Technologies
2
Byte Enables from EBUS Configuration Descriptor
ALAPSE = 0
3
Address
4
(11)
5
ELAPSE = 0
®
Electrical and Mechanical Specification
Data
6
7
8
BLAPSE = 0
9
10
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