cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 190

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table A-5.
A.14
Tables A-6
show similar results for three types of configuration, where all channels within each type are configured exactly the
same, per the column heading. The only difference between
increases from zero to two. This highlights the impact of a small increase in PCI latency.
a fourth system configuration that combines two different channel configurations (T1 payload and overhead)
operating simultaneously.
Since
device system is approximately double what is shown on the following pages.
A.15
Refer to
1. Memory Available is apportioned according to the rate at which the bits arrive on that channel. Hence a
28500-DSH-002-C
MAXDATA
Max L
Max L
Max L
Max L
Utilization–RX
Utilization–TOTAL
Amnt data filled in L
Amnt data filled in L
combination of high-speed channels and low-speed channels yields a different amount of buffering allocated to
channels in the third example.
ch
pci
ch
pci
Tables A-6
Variable Name
(ms) RX
(ms) TX
(ms) RX
(ms) TX
Tables A-6
through
Non –“Spare Time” Calculations
pci-rx
pci-tx
through
Examples
Differences in the Combined T1 Payload and Overhead
Table
A-8
TX
RX
through
show calculated results for four different types of channel configuration.
A-8
Maximum amount of data that can be transferred across
the PCI from the internal FIFO.
Maximum amount of time a channel can endure without
a single data transaction before an overflow will occur.
Maximum amount of time the DMA will take from the
end of spare time until the first data transaction from a
specific channel.
Maximum amount of time a channel can wait without a
single data transaction before its internal SLP buffer will
be empty.
Maximum amount of time the DMA will take from the
end of spare time until the first data transaction to that
channel.
Average ratio of Host to CX28500 RX utilization of the
PCI.
Average ratio of Host to CX28500 utilization of the PCI.
Amount of data added to receive internal SLP buffers
during the maximum amount of time taken to reach it.
Amount of data removed from transmit internal SLP
buffers during the maximum amount of time taken to
reach it.
Tables
are calculated for only one CX28500 device, total PCI system utilization for a two-
A-8.
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Description
CX28500 PCI Bus Latency and Utilization Analysis
Tables A-6
®
Calculated (by iteration) taking into account amount
filled in while a channel waits to be serviced, and the
channel’s threshold; separate for receive and transmit
channels.
Calculated from threshold, buffer length, and internal
channel rate.
Calculated (by iteration) taking into account PCI bit
mode, PCI bit rate, MAXDATA, and packet transactions
of all channels.
Calculated from threshold, buffer length, and internal
channel rate.
Calculated (by iteration) taking into account PCI bit
mode, PCI bit rate, MAXDATA, and packet transactions
of all channels.
Amount of time taken to transfer one bit of RX data out
of CX28500 divided by the amount of time to transfer
one bit of receive data to the Host memory.
CX28500 Receive utilization plus CX28500 Transmit
utilization.
Calculated from internal channel rate and L
Calculated from internal channel rate and L
and
A-7
is the read latency (r value), which
Calculated
Table A-8
Tables A-6
gives results for
pci
pci
.
.
and
A-7
175