cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 58

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

As a PCI master, CX28500 generates the following PCI bus operations:
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3.1.3
Fast back-to-back transactions allow agents to utilize bus bandwidth more effectively. CX28500 supports PCI fast
back-to-back transactions both as a bus target and bus master. CX28500 can also execute fast back-to-back
transactions regardless of the PCI configuration settings (for details see bit 9 TARGET_FBTB bit field, in
20, Global Configuration
Fast back-to-back transactions are allowed on PCI when contention on TRDY*, DEVSEL*, STOP*, or PERR* is
avoided.
CX28500, as a master supporting fast back-to-back transactions, places the burden of avoiding contention on itself.
While acting as a slave, CX28500 places the burden on all the potential targets. As a master, CX28500 may
remove the Idle state between transactions when it can guarantee that no contention occurs. This can be
accomplished when the master’s current transaction is to the same target as the previous transaction. While
supporting this type of fast back-to-back transaction, CX28500 understands the address boundaries of the
potential target, so that no contention occurs. The target must be able to detect a new assertion of FRAME* without
the bus going to Idle state.
3.1.3.1
During a fast back-to-back transaction, the master starts the next transaction if GNT* is still asserted. If GNT* is
deasserted, the master has lost access to the bus and must relinquish the bus to the next master. The last data
phase completes when FRAME* is deasserted, and IRDY* and TRDY* (or STOP*) are asserted. The current
master starts another transaction on the clock following the completion of the last data phase of the previous
transaction. During fast back-to-back transaction, only the master and target involved need to distinguish
intermediate transaction boundaries using only FRAME* and IRDY* (there is no bus Idle state). When the
transaction is over, all the agents see an Idle state.
3.1.3.2
Appendix B
transactions shown are bursts of 2, 3, 4, 5, or 6 dwords read-write transferred while the address-data is either 32-
bit or 64-bit wide.
3.1.4
This section describes how CX28500 implements the required PCI configuration register space. The intent of PCI
configuration space definition is to provide an appropriate set of configuration registers that satisfy the needs of
current and anticipated system configuration mechanisms, without specifying those mechanisms or otherwise
placing constraints on their use. These registers allow for the following:
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28500-DSH-002-C
Memory Read
Memory Read Line
Memory Read Multiple (generated only in master mode)
Memory Write
Full device relocation, including interrupt binding
Installation, configuration, and booting without user intervention
System address map construction by device-independent software
shows an example of an arbitration for fast back-to-back and non-fast back-to-back transactions. The
Fast Back-to-Back Transactions
Operation Mode
Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-Back
Transactions
PCI Configuration Space
Descriptor).
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Host Interface
Table 6-
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