cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 98

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

6.3.1.1.1
The DMA interrupt descriptor is 69 bits wide, and the detailed description of its field is provided in
most significant bit in the DMA interrupt descriptor is always read as 0.
Table 6-17.
28500-DSH-002-C
63
62:58
57:48
47:43
42
41:40
39:38
37:36
Bit
Field Name
CH [9:0]
INT[1:0]
RSVD
RSVD
RSVD
RSVD
DMA Interrupt Descriptors Format (1 of 2)
TYP
DIR
DMA Interrupt Descriptor Format
Value
—
—
—
—
—
—
—
0
Interrupt descriptor type 0.
Reserved
The channel number causing the interrupt.
Reserved
0: Direction—receive
1: Direction—transmit
Reserved
0: RxEOB/TxEOB, (Receive or Transmit End Of Buffer)
This event is generated when current data buffer has been completely processed, and the EOBIEN bit
field is set in the associated Receive/ Transmit Buffer Descriptor. The EOB interrupt reports the correct
number of received transmitted bytes in BLEN field.
1: RxONR/TxONR–Generated when the next Buffer Descriptor is not available to CX28500 when
expected, the NP bit field in the buffer descriptor is set and the DMA is in the middle of a message, and
the ownership interrupt is enabled (bit field ONR in RDMA Channel Configuration register or TDMA
Channel Configuration register).
2: RxEOM–Generated when End Of Message occurs (even if errors were detected). If EOMIEN (bit field in
the Receive Buffer Descriptor) is enabled, an RxEOM is generated regardless the value of EOBIEN. In
other words, the EOM gets higher priority than an EOB event. An EOM interrupt reports the correct
number of received bytes in BLEN field.
Only when RxEOM = 1, which means an end of messages has been reported for that particular message
and the RxERR field is relevant.
3: RxEOCE/TxEOCE–End Of Command Execution generated after service request channel activation,
deactivation or jump.
Reserved
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Description
Memory Organization
Table
6-17. The
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