EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 100

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
4–30
Preliminary
Notes to
(1)
(2)
(3)
f
t
t
t
f
-
N, G0, G1, E
OUT
OUT
JITTER
LOCK
VCO
Table 4–52. Cyclone PLL Specifications (Part 2 of 2)
(to global clock)
DUTY
The t
of them are switching outputs, how much they toggle, and whether or not they use programmable current strength
or slow slew rate.
f
specification is 60 mUI.
f
operates with the specified parameters under the specified conditions.
OUT
IN/N
(3)
(1)
Table
Symbol
≥ 100 MHz. When the PLL external clock output frequency (f
JITTER
must be greater than 200 MHz to ensure correct lock detect circuit operation below –20 C. Otherwise, the PLL
specification for the PLL[2..1]_OUT pins are dependent on the I/O pins in its V
4–52:
PLL output frequency
(-6 speed grade)
PLL output frequency
(-7 speed grade)
PLL output frequency
(-8 speed grade)
Duty cycle for external clock
output (when set to 50%)
Period jitter for external clock
output
Time required to lock from end
of device configuration
PLL internal VCO operating
range
Minimum areset time
Counter values
Parameter
OUT
15.625
15.625
15.625
500.00
45.00
10.00
Min
10
) is smaller than 100 MHz, the jitter
1
±300
1,000
Max
405
320
275
100
55
32
CCIO
Altera Corporation
(2)
bank, how many
January 2007
integer
MHz
MHz
MHz
MHz
Unit
ps
μs
ns
%