EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 77

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
January 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Pin pull-up resistance values will lower if an external source drives the pin higher than V
(11) Drive strength is programmable according to values in
(12) Overdrive is possible when a 1.5 V or 1.8 V and a 2.5 V or 3.3 V input signal feeds an input pin. Turn on “Allow
(13) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels.
(14) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
C
C
C
C
C
Table 4–16. Cyclone Device Capacitance
IO
LVDS
VREF
DPCLK
CLK
Symbol
Refer to the Operating Requirements for Altera Devices Data Sheet.
Conditions beyond those listed in
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
Maximum V
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
powered.
Typical values are for T
V
This value is specified for normal device operation. The value may vary during power-up. This applies for all
V
R
will be lower if an external source drives the pin higher than V
voltage overdrive” for LVTTL/LVCMOS input pins in the Assignments > Device > Device and Pin Options > Pin
Placement tab when a device has this I/O combination. However, higher leakage current is expected.
accuracy is within ±0.5 pF.
I
CCIO
CONF
= ground, no load, no toggling inputs.
Tables 4–1
settings (3.3, 2.5, 1.8, and 1.5 V).
is the measured value of internal pull-up resistance when the I/O pin is tied directly to GND. R
CC
Input capacitance for user I/O pin
Input capacitance for dual-purpose LVDS/user I/O pin
Input capacitance for dual-purpose V
Input capacitance for dual-purpose
Input capacitance for CLK pin.
rise time is 100 ms, and V
through 4–16:
A
= 25° C, V
Table 4–1
CCINT
Parameter
CC
= 1.5 V, and V
must rise monotonically.
may cause permanent damage to a device. Additionally, device
Note (14)
DPCLK
R E F
CCIO
Chapter 2, Cyclone
/user I/O pin.
= 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
/user I/O pin.
C C I O
.
Architecture,
Typical
12.0
CCINT
4.0
4.7
4.4
4.7
Table
Operating Conditions
CCIO
.
and V
2–11.
CCIO
Preliminary
CONF
are
Unit
pF
pF
pF
pF
pF
value
4–7