EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 42

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
2–36
Preliminary
External Clock Inputs
Each PLL supports single-ended or differential inputs for source-
synchronous receivers or for general-purpose use. The dedicated clock
pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also
act as LVDS input pins. See
Table 2–8
pins.
For more information on LVDS I/O support, see
page
External Clock Outputs
Each PLL supports one differential or one single-ended output for source-
synchronous transmitters or for general-purpose external clocks. If the
PLL does not use these PLL_OUT pins, the pins are available for use as
general-purpose I/O pins. The PLL_OUT pins support all I/O standards
shown in
The external clock outputs do not have their own V
supplies. Therefore, to minimize jitter, do not place switching I/O pins
next to these output pins. The EP1C3 device in the 100-pin TQFP package
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
LVDS
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
SSTL-3 class II
Differential SSTL-2
Table 2–8. PLL I/O Standards
2–54.
I/O Standard
Table
shows the I/O standards supported by PLL input and output
2–8.
Figure
2–25.
CLK Input
v
v
v
v
v
v
v
v
v
v
“LVDS I/O Pins” on
CC
and ground voltage
Altera Corporation
EXTCLK Output
January 2007
v
v
v
v
v
v
v
v
v
v
v